1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor integrated circuit device of a standard cell system having improved power supply lines using three or more wiring layers.
2. Description of the Related Art
In recent years, micropatterning of elements has been rapidly developing as semiconductor process techniques are improved, and the number of elements integrated in one chip has been increased. As a result, the period required for designing a large scale integrated circuit has been undesirably increased. In order to shorten the designing period, a method of designing a standard cell system has been widely employed.
When an integrated circuit is designed according to a standard cell, a cell library including basic gates (such as an inverter, a NAND gate, and a flip-flop) pattern-designed in advance is used, and cells in the cell library are automatically arranged and wired by a computer in accordance with logical net list of the integrated circuit to obtain a desired layout of the integrated circuit. As described above, this design method for an integrated circuit using a standard cell system has the feature that the period required for layout is extremely short because cells designed in advance and registered as a cell library are used, and because the actual wiring operation is automatically performed by computer.
FIGS. 1 and 2 show a semiconductor integrated circuit device of a standard cell system according to the prior art, in which FIG. 1 is a plan view, and FIG. 2 is a perspective view of the device in FIG. 1. A plurality of cell arrays which are designed in advance ar aligned by a computer in accordance with logical connection data. Spaces between the cell arrays serve as wiring channels, and the cells are wired utilizing the wiring channels, thus constituting a predetermined integrated circuit. Only two standard cell arrays 12.sub.1 and 12.sub.2 are shown in FIGS. 1 and 2, for the sake of descriptive simplicity.
In this integrated circuit, a Vcc power supply line for supplying a power supply voltage to each standard cell in the standard cell arrays 12.sub.1 and 12.sub.2, and a GND power supply line to be grounded are arranged as follows.
When standard cells are arranged in one line to constitute a cell array, Vcc and GND power supply lines in a first aluminum (Al) layer which are designed in advance in the respective standard cells are arranged such that the Vcc power supply lines of adjacent standard cells are connected to each other, and the GND power supply lines of adjacent standard cells are also connected to each other. In FIG. 1, the Vcc and GND power supply lines in the standard cells are connected in the cell arrays 12.sub.1 and 12.sub.2 to form Vcc power supply lines 14.sub.1 and 14.sub.2 in the cell arrays, and GND power supply lines 16.sub.1 and 16.sub.2 in the cell arrays.
Signal lines are wired to the standard cells as follows. For example, a second aluminum (Al) layer is formed with first signal lines 18.sub.1 and 18.sub.2 in a direction perpendicular to the Vcc power supply lines 14.sub.1 and 14.sub.2 and the GND power supply lines 16.sub.1 and 16.sub.2. The first Al layer is formed with second signal lines 20.sub.1 and 20.sub.2 along the standard cell arrays 12.sub.1 and 12.sub.2. The second signal lines 20.sub.1 and 20.sub.2 are connected to the first signal lines 18.sub.1 and 18.sub.2 through via holes 22. The second signal line 20.sub.2 is connected to a polysilicon wiring layer 26 through a contact hole 24. The polysilicon wiring layer 26 is connected to one of the standard cells having a predetermined logical function. A supply bus for supplying a power supply voltage is arranged to operate the standard cells in the standard cell arrays 12.sub.1 and 12.sub.2. More specifically, the second Al layer is formed with Vcc power supply buses 28.sub.1 and 28.sub.2 and GND power supply buses 30.sub.1 and 30.sub.2 --all made from the second Al layer--are arranged in a direction perpendicular to the Vcc power supply lines 14.sub.1 and 14.sub.2 and the GND power supply lines 16.sub.1 and 16.sub.2. These buses 28.sub.1, 28.sub.2, 30.sub.1, and 30.sub.2 are connected to the Vcc power supply lines 14.sub.1 and 14.sub.2 and the GND power supply lines 16.sub.1 and 16.sub.2 at the both ends thereof through via holes 32 and 34.
A current path of the semiconductor integrated circuit device of the standard cell system with the above arrangement is schematically shown in FIG. 3. In FIG. 3, a current from, e.g., the GND power supply line 16.sub.2 is supplied to the GND power supply buses 30.sub.1 and 30.sub.2 through the via holes 34, as indicated by arrows. Similarly, a current from the GND power supply line 16.sub.1 is supplied to the GND power supply buses 30.sub.1 and 30.sub.2 through the via holes 34.
In the above-mentioned integrated circuit of a standard cell system according to the prior art, when a large scale circuit is arranged, the number of cells arranged in one cell array is increased, and a current which flows through the power supply lines in the cell array is increased, thus causing electromigration. Since the width of each power supply line arranged in the cell is designed in advance and fixed, the number of cells arranged in one cell array is limited so that the current has an allowable density or less of a current which can flow through the power supply line.
When a high-speed operation for decreasing the scale of an integrated circuit is achieved by a scaling operation using a designed standard cell library, the width of the power supply line in the cell array is decreased, and hence the current density of current in the supply line is increased, thus causing electromigration.
Note that electromigration is a phenomenon by which a void or a hillock is formed in a metal layer when metal ions in the metal wiring layers are moved under the condition of a large current density, thus finally causing disconnection or short-circuiting of the lines. The service life of each line is adversely affected, and the service life of the integrated circuit device is shortened.
In order to solve the above problem, each line must be reinforced to withstand a large current density. For example, when the widths (patterns) of the Vcc power supply buses 28.sub.1 and 28.sub.2 and the GND power supply buses 30.sub.1 and 30.sub.2 arranged on the standard cell arrays 12.sub.1 and 12.sub.2 are increased, the above problem can be solved.
However, if the widths of the Vcc power supply lines 14.sub.1 and 14.sub.2 and the GND power supply lines 16.sub.1 and 16.sub.2 arranged in the standard cell arrays 12.sub.1 and 12.sub.2 are similarly increased, logic patterns in the standard cells are adversely affected. More specifically, when the pattern power supply lines are made broader, the standard cells will become larger, inevitably reducing the integration density of the circuit. An increase in the width of these lines is a bar to the enhancement of the integration density.